L640DU21NF datasheet(13/57 Pages) AMD

13 / 57 page

January 22, 2007 22366C6

Am29LV640D/Am29LV641D

D A TA

SH EE T

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

See “Requirements for Reading Array Data” on

page 10 for more infor mation. Refer to the AC

“Read-Only Operations” on page 37 table for timing

specifications and to Figure 13, on page 37 for the tim-

ing diagram. I

CC1 in the “DC Character i stics” on

page 34 table represents the active current specifica-

tion for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V

IL, and OE# to VIH.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word instead of four. The “Word

Program Command Sequence” on page 24 has de-

tails on programming data to the device using both

standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 on page 12 indicates

the address space that each sector occupies.

CC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This function is primarily in-

tended to allow faster manufacturing throughput dur-

ing system production.

If the system asserts V

HH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

HH from the ACC pin returns the device to normal op-

eration. Note that the ACC pin must not be at V

HH for

operations other than accelerated programming, or

device damage may result.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the “Autoselect Mode” on page 16

and “Autoselect Command Sequence” on page 24 for

more information.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V

CC ± 0.3 V.

(Note that this is a more restricted voltage range than

IH.) If CE# and RESET# are held at VIH, but not within

CC ± 0.3 V, the device is in the standby mode, but the

standby current is greater. The device requires stan-

dard access time (t

CE) for read access when the de-

vice is in either of these standby modes before it is

ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

CC3 in the table “DC Characteristics” on page 34 rep-

resents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC +

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

CC4 in the table “DC Characteristics” on page 34 rep-

resents the automatic sleep mode current specifica-

tion.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t

RP, the

device immediately ter minates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. To ensure data integrity,

the operation that was interrupted should be reinitiated

once the device is ready to accept another command

sequence.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V

SS±0.3 V, the device

draws CMOS standby current (I

CC4). If RESET# is held

at V

IL but not within VSS±0.3 V, the standby current is

greater.

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