LTM4712

14

Rev. 0

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A graphical representation of the aforementioned ther-

mal resistances is given in Figure 2; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the μModule.

As a practical matter, it should be clear that no individual

or sub-group of the four thermal resistance parameters

defined by JESD 51-12 or provided in the Pin Configuration

section replicates or conveys normal operating conditions

of a μModule. For example, in normal board-mounted

applications, never does 100% of the device’s total power

loss (heat) thermally conduct exclusively through the top

or exclusively through bottom of the μModule—as the

standard defines for θJCtop and θJCbottom, respectively.

In practice, power loss is thermally dissipated in both

directions away from the package. Granted, in the absence

of a heat sink and airflow, a majority of the heat flow is

into the board.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the μModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JSED 51-9 to predict power loss heat flow.

APPLICATIONS INFORMATION

JUNCTION

AMBIENT

Module DEVICE

4712 F02

θJCtop, JUNCTION-TO-CASE (TOP)

RESISTANCE

θJB, JUNCTION-TO-BOARD RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

θJCbot, JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

θJA, JUNCTION-TO-AMBIENT RESISTANCE

Figure 2. Graphical Representation of Thermal Coefficients, Including JESD51-12 Terms