X28HT010 datasheet(3/20 Pages) INTERSIL

3 / 20 page

FN8105.1

February 12, 2007

Block Diagram

Pin Descriptions

Addresses (A0-A16)

The Address inputs select an 8-bit memory location during a

read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/write

operations. When CE is HIGH, power consumption is

reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers,

and is used to initiate read operations.

Data In/Data Out (I/O0-I/O7)

Data is written to or read from the X28C010/X28HT010

through the I/O pins.

Write Enable (WE)

The Write Enable input controls the writing of data to the

X28C010/X28HT010.

Back Bias Voltage (VBB) (X28HT010 only)

It is required to provide -3V on pin 1. This negative voltage

improves higher temperature functionality.

Device Operation

Read

Read operations are initiated by both OE and CE LOW. The

read operation is terminated by either CE or OE returning

HIGH. This two line control architecture eliminates bus

contention in a system environment. The data bus will be in

a high impedance state when either OE or CE is HIGH.

Write

Write operations are initiated when both CE and WE are

LOW and OE is HIGH. The X28C010/X28HT010 supports

both a CE and WE controlled write cycle. That is, the

address is latched by the falling edge of either CE or WE,

whichever occurs last. Similarly, the data is latched internally

by the rising edge of either CE or WE, whichever occurs first.

A byte write operation, once initiated, will automatically

continue to completion, typically within 5ms.

X Buffers

Latches and

Decoder

I/O Buffers

and Latches

Y Buffers

Decoder

Control

Logic and

Timing

1Mbit

EEPROM

Array

I/O0-I/O7

Data Inputs/Outputs

VCC

VSS

A0-A7

Latches and

A8-A16

Pin Names

SYMBOL

DESCRIPTION

A0-A16

Address Inputs

I/O0-I/O7

Data Input/Output

Write Enable

Chip Enable

Output Enable

VCC

+5V

VSS

Ground

No Connect

VBB*-3V

*VBB applies to X28HT010 only.

X28C010, X28HT010

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