CDCL6010 datasheet(14/27 Pages) TI

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CDCL6010

SLLS780 – FEBRUARY 2007

Power Up

Bit

Bit Name

Description/Function

Type

Condition

Reference To

ENDRV3

YP[3], YN[3] enable; if 0 output is disabled

R/W

ENDRV2

YP[2], YN[2] enable; if 0 output is disabled

R/W

ENDRV1

YP[1], YN[1] enable; if 0 output is disabled

R/W

ENDRV0

YP[0], YN[0] enable; if 0 output is disabled

R/W

SELBW[3]

PLL BW select; if 1 external loop filter is expected

R/W

Table 6

SELBW[2]

PLL BW select; if 1 external loop filter is expected

R/W

Table 6

SELBW[1]

PLL BW select; if 1 external loop filter is expected

R/W

Table 6

SELBW[0]

PLL BW select; if 1 external loop filter is expected

R/W

Table 6

Bit

Power Up

Bit

Name

Description/Function

Type

Condition

Reference To

ENPLL

PLL enable; if 0 PLL is switched off

R/W

RES

Reserved

R/W

SELM[1]

Divide ratio select for input clock CLKP and CLKN

R/W

Table 3

SELM[0]

Divide ratio select for input clock CLKP and CLKN

R/W

Table 3

SELN[3]

Divide ratio select for pre-divider N (PLL clock)

R/W

Table 2

SELN[2]

Divide ratio select for pre-divider N (PLL clock)

R/W

Table 2

SELN[1]

Divide ratio select for pre-divider N (PLL clock)

R/W

Table 2

SELN[0]

Divide ratio select for pre-divider N (PLL clock)

R/W

Table 2

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