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3.8 Device Initialization Sequence After Reset

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Software should follow this initialization sequence after coming out of device reset.

1. Complete the boot sequence as needed. For more details on the boot sequence, see the Using the

TMS320C642x Bootloader Application Report (literature number SPRAAK5).

2. If the device is not already at the desired operating frequency, program the PLL Controllers (PLLC1

and PLLC2) to configure the device frequency. For details on how to program the PLLC, see the

C642x DSP Phase-Locked Loop Controller (PLLC) User's Guide (literature number SPRUES0).

3. Program PINMUX0 and PINMUX1 registers to select device pin functions. For more details on

programming the PINMUX0 and PINMUX1 registers to select device pin functions, see Section 3.7,

Multiplexed Pin Configurations.

Note: If EMAC operation is desired, the EMAC must be placed in reset before programming

PINMUX1.HOSTBK and PINMUX1.RMII to select EMAC pins.

4. Program the VDD3P3V_PWDN register to power up the necessary I/O pins. For more details on

programming the VDD3P3V_PWDN register, see Section 3.2, Power Considerations.

5. As needed by the application, program the following System Module registers when there are no active

transactions on the respective peripherals:

HPICTL (Section 3.6.2.1, HPI Control Register): applicable for HPI only if a different host burst

write timeout value from default is desired.

TIMERCTL (Section 3.6.2.2, Timer Control Register): applicable for Timer0 and Watchdog Timer2

only.

EDMATCCFG (Section 3.6.2.3, EDMA TC Configuration Register): applicable for EDMA only. The

recommendation is to leave the EDMATCCFG register at its default.

6. Program the Power and Sleep Controller (PSC) to enable the desired peripherals. For details on how

to program the PSC, see the TMS320C642x Power and Sleep Controller (PSC) User's Guide

(literature number SPRUEN8).

7. Program the Switched Central Resource (SCR) bus priorities for the master peripherals

(Section 3.6.1). This must be configured when there are no active transactions on the respective

peripherals:

Program the MSTPRI0 and MSTPRI1 registers in the System Module. These registers can be

programmed before or after the respective peripheral is enabled by the PSC in step 6.

Program the EDMACC QUEPRI register, the C64x+ MDMAARBE.PRI field. These registers can

only be programmed after the respective peripheral is enabled by the PSC in step 6.

8. Configure the C64x+ Megamodule and the peripherals.

For details on C64x+ Megamodule configuration, see the TMS320C64x+ DSP Megamodule

Reference Guide (literature number SPRU871).

Special considerations 1: C64x+ L1P and L1D cache– on the C6421 device, the L1P

Configuration Register (L1PCFG) and the L1D Configuration Register (L1DCFG) are

device-specific and vary from what is shown in the TMS320C64x+ DSP Megamodule

Reference Guide (SPRU871). For more details on theC6421 L1PCFG and L1DCFG register

definitions, see Section 2.2.2,C64x+ Memory Architecture. In this step, the user must modify

the L1PMODE and L1DMODE settings to a valid setting (0, 1h, 2h, or 3h) by following these

steps:

Write the desired L1P cache mode to the L1PMODE field in the L1PCFG register. Valid

L1PMODE settings are as follows: 0h (Cache disabled), 1h (4KB L1P cache), 2h (8KB L1P

cache), or 3h (16KB L1P cache).

ii.

Read back L1PCFG. This stalls the CPU until the mode change completes.

iii. Write the desired L1D cache mode to the L1DMODE field in the L1DCFG register. Valid

L1DMODE settings are as follows: 0h (Cache disabled), 1h (4KB L1D cache), 2h (8KB

L1D cache), or 3h (16KB L1D cache).

iv. Read back L1DCFG. This stalls the CPU until the mode change completes.

Device Configurations

108

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