TMS320C6421 datasheet(109/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

ii.

Special considerations 2: Bootloader disables C64x+ cache—For all boot modes that default

to DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot,

BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2,

L1P, and L1D) so that upon exit from the bootloader code, all C64x+ memories are configured

as all RAM (L2CFG.L2MODE = 0h, L1PCFG.L1PMODE = 0h, and L1DCFG.L1DMODE = 0h).

If cache use is required, the application code must explicitly enable the cache. For more

information on boot modes, see Section 3.4.1, Boot Modes. For more information on the

bootloader, see the Using the TMS320C642x Bootloader Application Report (literature number

SPRAAK5).

Peripherals configuration: see the respective peripheral user’s guide.

Special considerations: DDR2 memory controller—the Peripheral Bus Burst Priority Register

(PBBPR) should be programmed to ensure good DDR2 throughput and to prevent command starvation

(prevention of certain commands from being processed by the DDR2 memory controller). For more

details, see the TMS320C642x DSP DDR2 Memory Controller User's Guide (literature number

SPRUEM4). A hex value of 0x20 is recommended for the PBBPR PR_OLD_COUNT field to provide a

good DSP performance and still allow good utilization by other modules.

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Device Configurations

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TMS320C6421 Datasheet(PDF) 109 Page - Texas Instruments