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6.3.4

C6421 Power and Clock Domains

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

As with the selection of any component, verification of capacitor availability over the product's production

lifetime should be considered.

For more details on capacitor usage and placement, see the Implementing DDR2 PCB Layout on the

TMS320C642x Application Report (literature number SPRAAK5).

The C6421 includes one single power domain — the "Always On" power domain. The "Always On" power

domain is always on when the chip is on. The "Always On" domain is powered by the CVDD pins of the

C6421. All C6421 modules lie within the "Always On" power domain. Table 6-1 provides a listing of the

C6421 clock domains.

One primary reference clock is required for the C6421 device. It can be either a crystal input or driven by

external oscillators. A 15–30-MHz crystal is recommended for the PLLs, which generate the internal clocks

for the digital signal processor (DSP), peripherals, and the EDMA3. For further description of the C6421

clock domains, see Table 6-2 and Figure 6-4.

The C6421 architecture is divided into the power and clock domains shown in Table 6-1. Table 6-2 and

Table 6-3further discuss the clock domains and their ratios. Figure 6-4 shows the clock domain block

diagram.

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TMS320C6421 Datasheet(PDF) 119 Page - Texas Instruments