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6.5.4

CPU Local Reset

6.5.5

Peripheral Local Reset

6.5.6

Reset Priority

6.5.7

Reset Controller Register

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

The C64x+ DSP CPU has an internal reset input that allows a host (HPI) to control it. This reset is

configured through a register bit (MDCTL[39].LRST) in the Power Sleep Controller (PSC) module. When in

C64x+ local reset, the slave DMA port on C64x+ will remain active and the internal memory will be

accessible. For procedures on asserting and de-asserting CPU local reset by the host, see TMS320C642x

Power and Sleep Controller (PSC) Reference Guide (literature number SPRUEN8).

For information on peripheral selection at the rising edge of POR or RESET, see Section 3, Device

Configurations of this data manual.

The user can configure the local reset and clock state of a peripheral through programming the PSC.

Table 6-4, C6421 LPSC Assignments identifies the LPSC numbers and the peripherals capable of being

locally reset by the PSC. For more detailed information on the programming of these peripherals by the

PSC, see the TMS320C642x Power and Sleep Controller (PSC) Reference Guide (literature number

SPRUEN8).

If any of the above reset sources occur simultaneously, the PLLC only processes the highest priority reset

request. The rest request priorities are as follows (high to low):

• Power-on Reset

• Maximum Reset

• Warm Reset

• CPU Reset

The reset type status (RSTYPE) register (01C4 00E4) is the only register for the reset controller. This

Controller Registers (Including Reset Controller). For more details on the RSTYPE register, see

theTMS320C642x DSP Phase-Locked Loop Controller (PLLC) User's Guide (literature number

SPRUES0).

Peripheral Information and Electrical Specifications

142

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