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6.5.9

Reset Electrical Data/Timing

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Note: If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD)

resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor.

Table 6-11. Timing Requirements for Reset (see Figure 6-7 and Figure 6-8)

-400

-500

NO.

UNIT

-600

MIN

MAX

tw(RESET)

Pulse duration, POR low or RESET low

12C(1)

Setup time, boot and configuration pins valid before POR high or RESET

tsu(CONFIG)

12C(1)

high(2)

Hold time, boot and configuration pins valid after POR high or RESET

th(CONFIG)

high(2)

(1)

C = 1/MXI clock frequency in ns. The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET)

requirement.

(2)

For the list of boot and configuration pins, see Table 2-7, Boot Terminal Functions.

Table 6-12. Switching Characteristics Over Recommended Operating Conditions During Reset

(1)

(see Figure 6-8)

-400

-500

NO.

PARAMETER

UNIT

-600

MIN

MAX

td(RSTH-RSTOUTH)

Delay time, POR high or RESET high to RESETOUT high

1900C

tw(PAUSE)

Pulse duration, SYSCLKs paused (low) before RESETOUT high

10C

td(RSTL-IV)

Delay time, POR low or RESET low to pins invalid

td(RSTH-V)

Delay time, POR high or RESET high to pins valid

td(RSTOUTH-V)

Delay time, RESETOUT high to pins valid

td(RSTOUTH-IV)

Delay time, RESETOUT high to pins invalid

12C

(1)

C = 1/CLKIN1 clock frequency in ns.

Figure 6-7 shows the Power-Up Timing. Figure 6-8 shows the Warm Reset (RESET) Timing and Max

Reset Timing are identical to Warm Reset Timing, except the boot and configuration pins are not

relatched and the BOOTCFG register retains its previous value latched before the Max Reset were

initiated.

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