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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 6-15. PLLC1 Clock Frequency Ranges

CLOCK SIGNAL NAME

MIN

MAX

UNIT

MXI/CLKIN(1)

MHz

At 1.2-V CVDD

400

600

MHz

PLLOUT

At 1.05-V CVDD

400

520

MHz

-600 devices

600

MHz

SYSCLK1 (CLKDIV1 Domain)

-500 devices

500

MHz

-400 devices

400

MHz

(1)

MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).

Table 6-16. PLLC2 Clock Frequency Ranges

CLOCK SIGNAL NAME

MIN

MAX

UNIT

MXI/CLKIN(1)

MHz

At 1.2-V CVDD

400

900

MHz

PLLOUT

At 1.05-V CVDD

400

666

MHz

PLL2_SYSCLK1 (to DDR2 PHY)

333

MHz

(1)

MXI/CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2).

Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed.

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to

become stable after the PLL is powered up (after PLLCTL.PLLPWRDN bit goes through a 1-to-0

transition). The PLL should not be operated until this stabilization time has expired. This stabilization step

must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the

PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabilization time value, see Table 6-17.

The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 0)

before bringing the PLL out of reset (writing PLLRST = 1). For the PLL reset time value, see Table 6-17.

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1

with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the

PLL lock time value, see Table 6-17.

Table 6-17. PLL1 and PLL2 Stabilization, Lock, and Reset Times

PLL STABILIZATION/LOCK/RESET

MIN

TYP

MAX

UNIT

TIME

PLL Stabilization Time

150

µs

PLL Lock Time

2000C(1)

PLL Reset Time

128C(1)

(1)

C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 25 MHz, use C = 40 ns.

For details on the PLL initialization software sequence, see the TMS320C642x DSP Phase-Locked Loop

Controller (PLLC) User's Guide (literature number SPRUES0).

For more information on the clock domains and their clock ratio restrictions, see Section 6.3.4, C6421

Power and Clock Domains.

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