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6.7.3

Clock PLL Considerations with External Clock Sources

6.7.4

Clock PLL Electrical Data/Timing (Input and Output Clocks)

MXI/CLKIN

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

If the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power

both the C6421 device and the external clock oscillator circuit. The minimum CLKIN rise and fall times

should also be observed. For the input clock timing requirements, see Section 6.7.4, Clock PLL Electrical

Data/Timing (Input and Output Clocks).

Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock

source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Case Temperature and Section 6.7.4,

Clock PLL Electrical Data/Timing (Input and Output Clocks).

Table 6-19. Timing Requirements for MXI/CLKIN (-400, -500, -600) Devices

(1) (2) (3) (4) (see Figure 6-12)

-400

-500

NO.

UNIT

-600

MIN

MAX

tc(MXI)

Cycle time, MXI/CLKIN

33.3

66.7

tw(MXIH)

Pulse duration, MXI/CLKIN high

0.45C

0.55C

tw(MXIL)

Pulse duration, MXI/CLKIN low

0.45C

0.55C

tt(MXI)

Transition time, MXI/CLKIN

0.05C

tJ(MXI)

Period jitter, MXI/CLKIN

0.02C

(1)

The MXI/CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range

for CPU operating frequency. For example, for a -600 speed device with a 25 MHz CLKIN frequency, the PLL multiply factor should be

≤ 24.

(2)

The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

(3)

For more details on the PLL multiplier factors, see TMS320C642x DSP Phase-Locked Loop Controller (PLLC) User's Guide (literature

number SPRUES0).

(4)

C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 30 MHz, use C = 33.3 ns.

Figure 6-12. MXI/CLKIN Timing

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