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DDR_CLK0

6.10 Universal Asynchronous Receiver/Transmitter (UART)

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

6.9.4.1 DDR2 Memory Controller Electrical Data/Timing

The Implementing DDR2 PCB Layout on the C642x Digital Signal Processor application report (literature

number TBD) specifies a complete DDR2 interface solution for the C6421 as well as a list of compatible

DDR2 devices. TI has performed the simulation and system characterization to ensure all DDR2 interface

timings in this solution are met.

TI only supports board designs that follow the guidelines outlined in the Implementing DDR2 PCB Layout

on the C642x Digital Signal Processor application report (literature number TBD).

Table 6-27. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory

Controller

(1) (2)(see Figure 6-18)

-400

-500

NO.

PARAMETER

UNIT

-600

MIN

MAX

tc(DDR_CLK0)

Cycle time, DDR_CLK0

(1)

DDR_CLK0 cycle time = 2 x PLL2 _SYSCLK1 cycle time.

(2)

The PLL2 Controller must be programmed such that the resulting DDR_CLK0 clock frequency is within the specified range.

Figure 6-18. DDR2 Memory Controller Clock Timing

C6421 has 1 UART peripheral (UART0). UART0 has the following features:

• 16-byte storage space for both the transmitter and receiver FIFOs

• 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA

• DMA signaling capability for both received and transmitted data

• Programmable auto-rts and auto-cts for autoflow control

• Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates

• Prioritized interrupts

• Programmable serial data formats

–

5, 6, 7, or 8-bit characters

–

Even, odd, or no parity bit generation and detection

–

1, 1.5, or 2 stop bit generation

• False start bit detection

• Line break generation and detection

• Internal diagnostic capabilities

–

Loopback controls for communications link fault isolation

–

Break, parity, overrun, and framing error simulation

• Modem control functions (CTS, RTS) on

The UART0 register is listed in Table 6-28.

Peripheral Information and Electrical Specifications

166

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