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EM_CS[5:2]

EM_BA[1:0]

EM_A[21:0]

EM_OE

EM_D[7:0]

EM_WE

EM_R/W

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 6-25. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for EMIFA Module (see Figure 6-14 and Figure 6-15) (continued)

-400

-500

NO.

PARAMETER

UNIT

-600

MIN

MAX

(WST + 1) * E -

EM_WE active low width (EW = 0)

(WST + 1) * E + TBD

TBD

tw(EMWEL)

(WST + 1) * E -

EM_WE active low width (EW = 1)

(WST + 4097) * E + TBD

TBD

td(EMWAITH-EMWEH)

Delay time from EM_WAIT deasserted to EM_WE high

4E + TBD

tsu(EMDV-EMWEL)

Output setup time, EM_D[7:0] valid to EM_WE low

(WS + 1) * E - TBD

(WS + 1) * E + TBD

th(EMWEH-EMDIV)

Output hold time, EM_WE high to EM_D[7:0] invalid

(WH + 1) * E - TBD

(WH + 1) * E + TBD

Figure 6-14. Asynchronous Memory Read Timing for EMIF

Peripheral Information and Electrical Specifications

162

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