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TMS320C6421 Datasheet(PDF) 161 Page - Texas Instruments

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Part # TMS320C6421
Description  Fixed-Point Digital Signal Processor
PDF  227 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320C6421 Datasheet(HTML) 161 Page - Texas Instruments

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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346B – JANUARY 2007 – REVISED APRIL 2007
Table 6-25. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module
(1) (2) (see Figure 6-14 and Figure 6-15)
-400
-500
NO.
PARAMETER
UNIT
-600
MIN
MAX
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA + 1) * E - TBD
(TA + 1) * E + TBD
ns
READS
(RS + RST + RH) *
(RS + RST + RH) * E +
EMIF read cycle time (EW = 0)
ns
E - TBD
TBD
3
tc(EMRCYCLE)
(RS + RST + RH) *
EMIF read cycle time (EW = 1)
4188 * E + TBD
ns
E - TBD
Output setup time, EM_CS[5:2] low to EM_OE low (SS
(RS + 1) * E - TBD
(RS + 1) * E + TBD
ns
= 0)
4
tsu(EMCSL-EMOEL)
Output setup time, EM_CS[5:2] low to EM_OE low (SS
TBD
ns
= 1)
Output hold time, EM_OE high to EM_CS[5:2] high
(RH + 1) * E - TBD
(RH + 1) * E + TBD
ns
(SS = 0)
5
th(EMOEH-EMCSH)
Output hold time, EM_OE high to EM_CS[5:2] high
TBD
ns
(SS = 1)
6
tsu(EMBAV-EMOEL)
Output setup time, EM_BA[1:0] valid to EM_OE low
(RS + 1) * E - TBD
(RS + 1) * E + TBD
ns
7
th(EMOEH-EMBAIV)
Output hold time, EM_OE high to EM_BA[1:0] invalid
(RH + 1) * E - TBD
(RH + 1) * E + TBD
ns
8
tsu(EMBAV-EMOEL)
Output setup time, EM_A[21:0] valid to EM_OE low
(RS + 1) * E - TBD
(RS + 1) * E + TBD
ns
9
th(EMOEH-EMBAIV)
Output hold time, EM_OE high to EM_A[21:0] invalid
(RH + 1) * E - TBD
(RH + 1) * E + TBD
ns
(RST + 1) * E -
EM_OE active low width (EW = 0)
(RST + 1) * E + TBD
ns
TBD
10
tw(EMOEL)
(RS + RST + RH) *
EM_OE active low width (EW = 1)
(RST + 4087) * E + TBD
ns
E - TBD
11
td(EMWAITH-EMOEH)
Delay time from EM_WAIT deasserted to EM_OE high
4E + TBD
ns
WRITES
(RS + RST + RH) *
(RS + RST + RH) * E +
EMIF write cycle time (EW = 0)
ns
E - TBD
TBD
15
tc(EMWCYCLE)
(RS + RST + RH) *
EMIF write cycle time (EW = 1)
4188 * E + TBD
ns
E - TBD
Output setup time, EM_CS[5:2] low to EM_WE low
(WS + 1) * E - TBD
(WS + 1) * E + TBD
ns
(SS = 0)
16
tsu(EMCSL-EMWEL)
Output setup time, EM_CS[5:2] low to EM_WE low
TBD
ns
(SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high
(WH + 1) * E - TBD
(WH + 1) * E + TBD
ns
(SS = 0)
17
th(EMWEH-EMCSH)
Output hold time, EM_WE high to EM_CS[5:2] high
TBD
ns
(SS = 1)
18
tsu(EMRNW-EMWEL)
Output setup time, EM_R/W valid to EM_WE low
(WS + 1) * E - TBD
(WS + 1) * E + TBD
ns
19
th(EMWEH-EMRNW)
Output hold time, EM_WE high to EM_R/W invalid
(WH + 1) * E - TBD
(WH + 1) * E + TBD
ns
20
tsu(EMBAV-EMWEL)
Output setup time, EM_BA[1:0] valid to EM_WE low
(WS + 1) * E - TBD
(WS + 1) * E + TBD
ns
21
th(EMWEH-EMBAIV)
Output hold time, EM_WE high to EM_BA[1:0] invalid
(WH + 1) * E - TBD
(WH + 1) * E + TBD
ns
22
tsu(EMAV-EMWEL)
Output setup time, EM_A[21:0] valid to EM_WE low
(WS + 1) * E - TBD
(WS + 1) * E + TBD
ns
23
th(EMWEH-EMAIV)
Output hold time, EM_WE high to EM_A[21:0] invalid
(WH + 1) * E - TBD
(WH + 1) * E + TBD
ns
(1)
RS = Read setup, RST = Read STrobe, RH = Read Hold, WS = Write Setup, WST = Write STro`be, WH = Write Hold, TA = Turn
Around, EW = Extend Wait mode, SS = Select Strobe mode. These parameters are programmed via the Asynchronous Bank and
Asynchronous Wait Cycle Configuration Registers.
(2)
E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 600 MHz, use E = 10 ns.
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Peripheral Information and Electrical Specifications
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