TMS320C6421 datasheet(174/227 Pages) TI

174 / 227 page

www.ti.com

6.12.3 HPI Electrical Data/Timing

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 6-35. Timing Requirements for Host-Port Interface Cycles

(1) (2) (see Figure 6-23 through Figure 6-26)

-400

-500

NO.

UNIT

-600

MIN

MAX

tsu(SELV-HSTBL)

Setup time, select signals(3) valid before HSTROBE low

th(HSTBL-SELV)

Hold time, select signals(3) valid after HSTROBE low

tw(HSTBL)

Pulse duration, HSTROBE active low

tw(HSTBH)

Pulse duration, HSTROBE inactive high between consecutive accesses

tsu(SELV-HASL)

Setup time, select signals(3) valid before HAS low

th(HASL-SELV)

Hold time, select signals(3) valid after HAS low

tsu(HDV-HSTBH)

Setup time, host data valid before HSTROBE high

th(HSTBH-HDV)

Hold time, host data valid after HSTROBE high

Hold time, HSTROBE low after HRDY low. HSTROBE should not be

th(HRDYL-HSTBL)

inactivated until HRDY is active (low); otherwise, HPI writes will not

complete properly.

tsu(HASL-HSTBL)

Setup time, HAS low before HSTROBE low

th(HSTBL-HASL)

Hold time, HAS low after HSTROBE low

(1)

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(2)

M = SYSCLK3 period = (CPU clock frequency)/6 in ns. For example, when running parts at 600 MHz, use M = 10 ns.

(3)

Select signals include: HCNTL[1:0], HR/W and HHWIL.

Peripheral Information and Electrical Specifications

174

Submit Documentation Feedback

TMS320C6421 Datasheet(PDF) 174 Page - Texas Instruments

TMS320C6421 Datasheet(HTML) 174 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL