TMS320C6421 datasheet(182/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 6-39. Switching Characteristics Over Recommended Operating Conditions for McBSP

(1) (2)

(see Figure 6-27)

-400

-500

NO.

PARAMETER

UNIT

-600

MIN

MAX

Delay time, CLKS high to CLKR/X high for internal CLKR/X

td(CKSH-CKRXH)

generated from CLKS input

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

2P(3)(4)(5)

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X int

C - 1(6)

C + 1(6)

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR int

-4

5.5

CLKX int

-4

5.5

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

2.5

14.5

CLKX int

-5.5

7.5

Disable time, DX high impedance following

tdis(CKXH-DXHZ)

last data bit from CLKX high

CLKX ext

-2.1

CLKX int

-4 + D1(7)

5.5 + D2(7)

td(CKXH-DXV)

Delay time, CLKX high to DX valid

CLKX ext

2.5 + D1(7)

14.5 + D2(7)

Delay time, FSX high to DX valid

FSX int

-3.9(8)

5(8)

td(FXH-DXV)

ONLY applies when in data

FSX ext

-2.1(8)

5(8)

delay 0 (XDATDLY = 00b) mode

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

Minimum delay times also represent minimum output hold times.

(3)

Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times

are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.

(4)

P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10ns.

(5)

Use whichever value is greater.

(6)

C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK3 period)

S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).

(7)

Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 6P, D2 = 12P

(8)

Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 6P, D2 = 12P

Peripheral Information and Electrical Specifications

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