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TMS320C6421 Datasheet(PDF) 214 Page - Texas Instruments |
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TMS320C6421 Datasheet(HTML) 214 Page - Texas Instruments |
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214 / 227 page ![]() www.ti.com 6.19.2 VLYNQ Electrical Data/Timing VLYNQ_CLK 3 1 2 TMS320C6421 Fixed-Point Digital Signal Processor SPRS346B – JANUARY 2007 – REVISED APRIL 2007 Table 6-77. Timing Requirements for VLYNQ_CLK Input (see Figure 6-47) -400 -500 NO. UNIT -600 MIN MAX 1 tc(VCLK) Cycle time, VLYNQ_CLK 10 ns 2 tw(VCLKH) Pulse duration, VLYNQ_CLK high 3 ns 3 tw(VCLKL) Pulse duration, VLYNQ_CLK low 3 ns Table 6-78. Switching Characteristics Over Recommended Operating Conditions for VLYNQ_CLK Output (see Figure 6-47) -400 -500 NO. PARAMETER UNIT -600 MIN MAX 1 tc(VCLK) Cycle time, VLYNQ_CLK 10 ns 2 tw(VCLKH) Pulse duration, VLYNQ_CLK high 4 ns 3 tw(VCLKL) Pulse duration, VLYNQ_CLK low 4 ns Figure 6-47. VLYNQ_CLK Timing for VLYNQ Table 6-79. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the VLYNQ Module (see Figure 6-48) -400 -500 NO. PARAMETER UNIT -600 MIN MAX td(VCLKH- 1 Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] invalid 2.25 ns TXDI) td(VCLKH- 2 Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] valid 8.5 ns TXDV) Peripheral Information and Electrical Specifications 214 Submit Documentation Feedback |
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