Datasheet

7

002-34772 Rev. *F

2023-06-13

EZ-PD™ PAG2P primary-side startup controller

Functional description

3

Functional description

3.1

High voltage start-up

The line voltage is within normal operating range, then the gate driver starts switching. An internal high-voltage

JEFT take current from HV pin to charge up the VCC capacitor during start-up phase. An auxiliary winding from

the flyback transformer will be used to supply EZ-PD™ PAG2P after start-up phase and no current will be sourced

from the HV pin after start-up phase. Additionally, two modes are supported, namely, X-cap mode and non X-cap

mode. A VCC pin short protection is introduced. In the case of VCC pin shorted to ground, EZ-PD™ PAG2P shall limit

the startup current to maximum of I_HV_VCCSTG and avoid overheating of the IC.

3.1.1

X-cap mode

The HV pin of PAG2P is connected to the AC mains through diodes. A UVLO is included to prevent false startup

when the line voltage is low and keeps the primary FET OFF. An OVP is implemented to shut the primary FET OFF

when line voltage exceeds V_HV_OVRISE. PAG2P discharges the X-capacitor via HV pin when the X-cap mode is

enabled.

3.1.2

Non X-cap mode

The HV pin is connected to the DC rectified voltage. The pin powers PAG2P during startup. Additionally, it

provides under voltage and overvoltage protection via HV pin. As long as the fault is present, protection is

enabled.