Table 8-10. Registers 46 and 47 (Pull-Up/Pull-Down Enable Registers)

(continued)

BIT

PE-07

PE-06

PE-05

PE-04

PE-03

PE-02

PE-01

PE-00

DEFAULT

0

0

0

0

0

0

0

0

The pull-up/pull-down selection registers allow the user to configure each GPIO to have a pull-up or pull-down

resistor by programming the respective register bit. Setting a bit to a logic 1 selects a 100 kΩ pull-up resistor

for that GPIO pin. Setting a bit to logic 0 selects a 100 kΩ pull-down resistor for that GPIO pin. If the pull-up/

pull-down feature is disabled via registers 46 and 47, writing to these registers will have no effect on the GPIO

pin.

Table 8-11. Registers 48 and 49 (Pull-Up/Pull-Down Selection Registers)

BIT

PUD-07

PUD-06

PUD-05

PUD-04

PUD-03

PUD-02

PUD-01

PUD-00

DEFAULT

1

1

1

1

1

1

1

1

BIT

PUD-17

PUD-16

PUD-15

PUD-14

PUD-13

PUD-12

PUD-11

PUD-10

DEFAULT

1

1

1

1

1

1

1

1

The Interrupt mask registers are defaulted to logic 1 upon power-on, disabling interrupts during system start-up.

Interrupts may be enabled by setting corresponding mask bits to logic 0.

If an input changes state and the corresponding bit in the interrupt mask register is set to 1, the interrupt is

masked and the interrupt pin is not asserted. If the corresponding bit in the interrupt mask register is set to 0, the

interrupt pin will be asserted.

When an input changes state and the resulting interrupt is masked, setting the interrupt mask register bit to 0

causes the interrupt pin to be asserted. If the interrupt mask bit of an input that is already currently the source of

an interrupt is set to 1, the interrupt pin will be de-asserted.

Table 8-12. Registers 4A and 4B (Interrupt Mask Registers)

BIT

M-07

M-06

M-05

M-04

M-03

M-02

M-01

M-00

DEFAULT

1

1

1

1

1

1

1

1

BIT

M-17

M-16

M-15

M-14

M-13

M-12

M-11

M-10

DEFAULT

1

1

1

1

1

1

1

1

The Interrupt status registers are read only registers used to identify the source of an interrupt. When read, a

logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input

pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked),

the interrupt status bit will return to logic 0.

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TCAL9539

SCPS241 – JULY 2022

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