V

CC

V

POR

V

PORF

Time

POR

Time

Figure 9-9. VPOR

9.4 Layout

9.4.1 Layout Guidelines

For printed circuit board (PCB) layout of the TCAL9539, common PCB layout practices should be followed but

additional concerns related to high-speed data transfer such as matched impedance and differential pairs are not

a concern for I2C signal speeds.

In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from

each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher

amounts of current that commonly pass through power and ground traces. By-pass and decoupling capacitors

are commonly used to control the voltage on the supply pins, using a larger capacitor to provide additional power

in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These

capacitors should be placed as close to the TCAL9539 as possible. These best practices are shown in Figure

9-10.

For the layout example provided in Figure 9-10, it is possible to fabricate a PCB with only 2 layers by using the

top layer for signal routing and the bottom layer as a split plane for power and ground (GND). However, a 4 layer

board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals

on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer

to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly

next to the surface mount component pad which needs to attach to power or GND and the via is connected

electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be

routed to the opposite side of the board, but this technique is not demonstrated in Figure 9-10.

www.ti.com

TCAL9539

SCPS241 – JULY 2022

Copyright © 2022 Texas Instruments Incorporated

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