Table 8-13. Registers 4C and 4D (Interrupt Status Registers)

BIT

S-07

S-06

S-05

S-04

S-03

S-02

S-01

S-00

DEFAULT

0

0

0

0

0

0

0

0

BIT

S-17

S-16

S-15

S-14

S-13

S-12

S-11

S-10

DEFAULT

0

0

0

0

0

0

0

0

The output port configuration register selects port-wise push-pull or open-drain I/O stage. A logic 0 configures

the I/O as push-pull (Q1 and Q2 are active, see Figure 8-2). A logic 1 configures the I/O as open-drain (Q1 is

disabled, Q2 is active) and the recommended command sequence is to program this register (4F) before the

Configuration register (06 and 07) sets the port pins as outputs.

ODEN0 configures Port 0X and ODEN1 configures Port 1X.

Table 8-14. Register 4F (Output Port Configuration Register)

BIT

Reserved

ODEN-1 ODEN-0

DEFAULT

0

0

0

0

0

0

0

0

8.6.4 Bus Transactions

Data is exchanged between the controller and TCAL9539 through write and read commands.

8.6.4.1 Writes

Data is transmitted to the TCAL9539 by sending the device address and setting the least-significant bit (LSB) to

a logic 0 (see Figure 8-6 for device address). The command byte is sent after the address and determines which

register receives the data that follows the command byte. There is no limitation on the number of data bytes sent

in one write transmission.

Twenty-two registers within the TCAL9539 are configured to operate as eleven register pairs. The eleven pairs

are input port, output port, polarity inversion, configuration, output drive strength (two 16-bit registers), input

latch, pull-up/pull-down enable, pull-up/pulldown selection, interrupt mask, and interrupt status registers. After

sending data to one register, the next data byte is sent to the other register in the pair (see Figure 8-8 and Figure

8-9). For example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0

(register 2).

There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register

pair may be updated independently of the other registers.

1

2

SCL

3

4

5

6

7

8

SDA

A

A

A

Data 0

R/W

t

pv

9

0

0

0

0

0

0

0

1

0.7

0.0

Data 1

1.7

1.0 A

S

1

1

1

0

1

0

P

Target Address

Command Byte

Data to Port 0

Data to Port 1

Start Condition

Acknowledge

From Target

Write to Port

Data Out from Port 1

Data Out from Port 0

Data Valid

Acknowledge

From Target

Acknowledge

From Target

t

pv

Stop

Condition

A1 A0

Figure 8-8. Write to Output Port Register

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TCAL9539

SCPS241 – JULY 2022

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