AD9948KCPRL datasheet(8/28 Pages) AD

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AD9948

SYSTEM OVERVIEW

CCD

SERIAL

INTERFACE

DOUT

DIGITAL IMAGE

PROCESSING

ASIC

V-DRIVER

HD, VD

CLI

V1–Vx, VSG1–VSGx, SUBCK

H1–H4, RG

CCDIN

AD9948

INTEGRATED

AFE + TD

Figure 1. Typical Application

Figure 1 shows the typical system application diagram for the

AD9948. The CCD output is processed by the AD9948’s AFE

circuitry, which consists of a CDS, a PxGA, a VGA, a black level

clamp, and an A/D converter. The digitized pixel information is

sent to the digital image processor chip, where all postprocessing

and compression occurs. To operate the CCD, CCD timing

parameters are programmed into the AD9948 from the image

processor through the 3-wire serial interface. From the system

master clock, CLI, provided by the image processor, the AD9948

generates the high speed CCD clocks and all internal AFE clocks.

All AD9948 clocks are synchronized with VD and HD. All of

the AD9948’s horizontal pulses (CLPOB, PBLK, and HBLK)

are programmed and generated internally.

The H-drivers for H1–H4 and RG are included in the AD9948,

allowing these clocks to be connected directly to the CCD.

H-drive voltage of 3 V is supported in the AD9948.

Figure 2a shows the horizontal and vertical counter dimensions

for the AD9948. All internal horizontal clocking is programmed

using these dimensions to specify line and pixel locations.

MAXIMUM FIELD DIMENSIONS

12-BIT HORIZONTAL = 4096 PIXELS MAX

12-BIT VERTICAL = 4096 LINES MAX

Figure 2a. Vertical and Horizontal Counters

MAX VD LENGTH IS 4095 LINES

CLI

MAX HD LENGTH IS 4095 PIXELS

Figure 2b. Maximum VD/HD Dimensions

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