AD9948KCPRL datasheet(10/28 Pages) AD

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Table II. AFE Register Map

Data Bit

Default

Address

Content

Value

Name

Description

[11:0]

OPRMODE

AFE Operation Modes. (See Table VIII.)

[9:0]

VGAGAIN

VGA Gain.

[7:0]

CLAMP LEVEL

Optical Black Clamp Level.

[11:0]

CTLMODE

AFE Control Modes. (See Table IX.)

[17:0]

PxGA GAIN01

PxGA Gain Registers for Color 0 [8:0] and Color 1 [17:9].

[17:0]

PxGA GAIN23

PxGA Gain Registers for Color 2 [8:0] and Color 3 [17:9].

Table III. Miscellaneous Register Map

Data Bit

Default

Address

Content

Value

Name

Description

[0]

SW_RST

Software Reset.

1 = Reset all registers to default, then self-clear back to 0.

[0]

OUT_CONTROL

Output Control.

0 = Make all dc outputs inactive.

[0]

TGCORE_RSTB

Timing Core Reset Bar.

0 = Reset TG core.

1 = Resume operation.

[11:0]

UPDATE

Serial Update.

Sets the line (HD) within the field to update serial data.

[0]

PREVENTUPDATE

Prevents the update of the VD-Updated Registers.

1 = Prevent update.

[0]

VDHDEDGE

VD/HD Active Edge.

0 = Falling edge triggered.

1 = Rising edge triggered.

[1:0]

FIELDVAL

Field Value Sync.

0 = Next Field 0.

1 = Next Field 1.

2/3 = Next Field 2.

[0]

HBLKRETIME

Retime HBLK to Internal H1 Clock.

Preferred setting is 1. Setting to 1 will add one cycle delay to HBLK

toggle positions.

[1:0]

CLPBLKOUT

CLP/BLK Pin Output Select.

0 = CLPOB.

1 = PBLK.

2 = HBLK.

3 = Low.

[0]

CLPBLKEN

Enable CLP/BLK Output.

1 = Enable.

[0]

TEST MODE

Internal Test Mode.

Should always be set low.

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