SCANSTA111 datasheet(3/31 Pages) NSC

3 / 31 page

Architecture

Figure 1 shows the basic architecture of the ’STA111. The

device’s major functional blocks are illustrated here. The

TAP Controller, a 16-state state machine, is the central con-

trol for the device. The instruction register and various test

data registers can be scanned to exercise the various func-

tions of the ’STA111 (these registers behave as defined in

IEEE Std. 1149.1). The ’STA111 selection controller provides

the functionality that allows the 1149.1 protocol to be used in

a multi-drop environment. It primarily compares the address

input to the slot identification and enables the ’STA111 for

subsequent scan operations. The Local Scan Port Network

(LSPN) contains multiplexing logic used to select different

port configurations. The LSPN control block contains the

Local Scan Port Controllers (LSPC) for each Local Scan Port

(LSP

0, LSP1 ... LSPn). This control block receives input from

the ’STA111 instruction register, mode registers, and the TAP

controller. Each local port contains all four boundary scan

signals needed to interface with the local TAPs plus the

optional Test Reset signal (TRST).

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FIGURE 1. SCANSTA111 Block Diagram

SCANSTA111 Datasheet(PDF) 3 Page - National Semiconductor (TI)