SCANSTA111 datasheet(15/31 Pages) NSC

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Level 2 Protocol (Continued)

’STA111s connected to the backplane. The PARKPAUSE

instruction is scanned into the selected ’STA111s and the

’STA111 TAP controllers are sequenced to the Pause-DR

state where the LSPs of all ’STA111s become unparked. The

local TAP controllers are then sequenced through the

Update-DR, Select-DR, Capture-DR, Exit1-DR, and parked

in the Pause-DR state, as the ’STA111 TAP controller is

sequenced into the Update-DR state. When a LSP is parked,

it is removed from the active scan chain.

GOTOWAIT: This instruction is used to return all ’STA111s to

the Wait-For-Address state. All unparked LSPs will be

parked in the Test-Logic-Reset TAP controller state (see

Figure 5).

MODESEL: The MODESEL instruction inserts Mode Regis-

ter

0 into the active scan chain. Mode Register0 determines

the LSPN configuration for a device with up to five (5) LSPs

(only three in Silicon). Bit 7 of Mode Register

0 is a read-only

counter status flag.

MODESEL

n: The MODESELn instruction inserts Mode Reg-

ister

n (n = 1 to 3) into the active scan chain. Mode Register1

determines the LSPN configuration for LSP 5, 6 and 7 (if

they exist), and Mode Register

2 determines the Shared

GPIO configuration.

MCGRSEL: This instruction inserts the multi-cast group reg-

ister (MCGR) into the active scan chain. The MCGR is used

to group ’STA111s into multi-cast groups for parallel TAP

sequencing (i.e., to simultaneously perform identical scan

operations).

SOFTRESET: This instruction causes all 3 Port configura-

tion controllers (see Figure 4) to enter the Parked-TLR state,

which forces TMS

n high; this parks each local port in the

Test-Logic-Reset state within 5 TCK

B cycles.

LFSRSEL: This instruction inserts the linear feedback shift

pacted signature to be shifted out of the LFSR during the

Shift-DR state. (The signature is assumed to have been

computed during earlier LFSRON shift operations.) This in-

struction disables the LFSR register’s feedback circuitry,

turning the LFSR into a standard 16-bit shift register. This

allows a signature to be shifted out of the register, or a seed

value to be shifted into it.

LFSRON: Once this instruction is executed, the linear feed-

back shift register samples data from the active scan path

(including all unparked TDI

n) during the Shift-DR state. Data

from the scan path is shifted into the linear feedback shift

to be compressed into a 16-bit signature that can subse-

quently be shifted out using the LFSRSEL instruction. The

linear feedback shift register is not placed in the scan chain

during this mode. Instead, the register samples the active

scan-chain data as it flows from the LSPN to TDO

LFSROFF: This instruction terminates linear feedback shift

receiving this instruction.

CNTRSEL: This instruction inserts the 32-bit TCK counter

shift register into the active scan chain. This allows the user

to program the number of n TCK cycles to send to the parked

local ports once the CNTRON instruction is issued (e.g., for

BIST operations). Note that to ensure completion of count-

down, the ’STA111 should receive at least n TCK

B pulses.

CNTRON: This instruction enables the TCK counter. The

counter begins counting down on the first rising edge of

TCK

B following the Update-IR TAP controller state and is

decremented on each rising edge of TCK

B thereafter. When

the TCK counter reaches terminal count, 00000000 Hex,

TCK

n of all parked LSP’s is held low. This function overrides

Mode Register

0 TCK control bit (bit-3).

If the CNTRON instruction is issued when the TCK counter is

00000000 (terminal count) the local TCKs of parked LSPs

will be gated. The counter will begin counting on the rising

edge of TCK

B when the TCK counter is loaded with a non-

zero value following a CNTRSEL instruction (see BIST Sup-

port in Special Features section for an example).

CNTROFF: This instruction disables the TCK counter, and

TCK

n control is returned to Mode Register0 (bit-3).

DEFAULT_BYPASS: This instruction selects the Bypass

do not explicitly require a data register. The default after

RESET is the Device ID register.

10124512

FIGURE 9. Local Scan Port Synchronization from Parked-TLR State

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