TCS37209 datasheet(40/88 Pages) OSRAM

40 / 88 page

Datasheet, Public

Page 39

[v5-00] 2023-Nov-27

Document Feedback

TCS3720 − Register Overview

LDR1_CFG Register (Address 0x9B)

Figure 51:

LDR1_CFG Register

EYE_SAFETY_CFG Register (Address 0x9E)

Figure 52:

EYE_SAFETY_CFG Register

EYE_SAFETY_STATUS Register (Address 0x9F)

Figure 53:

EYE_SAFETY_STATUS Register

Addr: 0x9B

LDR1_CFG

Bit

Bit Name

Default

Access

Bit Description

Reserved

Reserved. Must be set to default value.

6EN_LDR_1

Enables the LDR1.

5:4

Reserved

Reserved. Must be set to default value.

3:0

PLDRIVE1

0010

This field sets the drive current of the VCSEL driver 1.

The formula is shown below:

Drive Current 1=PLDRIVE1 x ISINK_LSB.

Addr: 0x9E

EYE_SAFETY_CFG

Bit

Bit Name

Default

Access

Bit Description

EYE_SAFETY_

CHKS_ENAB

0RW

Enables VDD and VSS short check for PLDRIVE0, and also

the analog watch dog timer.

Eye safety runs only once at the beginning when PON

and PEN are enabled.

DISABLE_

PROX_ON_WD_

FAIL

1RW

Disable the high side switch when the eye safety watch

dog expires.

5:0

Reserved

Reserved. Must be set to default value.

Addr: 0x9F

EYE_SAFETY_STATUS

Bit

Bit Name

Default

Access

Bit Description

7:5

Reserved

Reserved. Must be set to default value.

EYE_SAFETY_

WD_STATUS_

SYNCED

When the flag is set, it indicates that the watchdog has

triggered.

When DISABLE_PROX_ON_WD_FAIL is set, the

PLDRIVER0 is disabled when this flag is set.

TCS37209 Datasheet(PDF) 40 Page - OSRAM GmbH

TCS37209 Datasheet(HTML) 40 Page - OSRAM GmbH

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL