AD5734R datasheet(6/20 Pages) AD

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AD5726

Rev. 0 | Page 6 of 20

TIMING CHARACTERISTICS

AVDD = +15 V/+5 V, AVSS = −15 V/−5 V/0 V, GND = 0 V; VREFP = +10 V/+2.5 V; VREFN = −10 V/−2.5 V/0 V, VL = 5 V, RLOAD = 2 kΩ,

CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.1, 2

Table 5.

Parameter

Limit at TMIN, TMAX

Unit

Description

tDS

Data setup time.

tDH

Data hold time.

tCH

Clock pulse width high.

tCL

Clock pulse width low.

tCSS

Select time.

tCSH

Deselect delay.

tLD1

Load disable time.

tLD2

Load delay.

tLDW

Load pulse width.

tCLRW

Clear pulse width.

1 Guaranteed by design and characterization, not production tested.

2 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

SDIN

SCLK

LDAC

tCSS

tLD1

tCSH

tLD2

D11

D10

Figure 2. Data Load Sequence

SDIN

SCLK

VOUT

LDAC

tDS

tCL

tCH

tCSH

tLD2

tLDW

tDH

±1LSB

Figure 3. Data Load Timing

CLRSEL

VOUT

CLR

tCLRW

±1LSB

Figure 4. Clear Timing

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