AD5734R datasheet(14/20 Pages) AD

14 / 20 page

AD5726

Rev. 0 | Page 14 of 20

SERIAL INTERFACE

The AD5726 is controlled over a versatile 3-wire serial interface

that operates at clock rates up to 30 MHz and is compatible with

SPI, QSPI™, MICROWIRE™, and DSP standards.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the

device MSB first as a 16-bit word under the control of a serial

clock input SCLK. The input register consists of two address

bits, two don’t care bits, and 12 data bits as shown in Table 11.

The timing diagram for this operation is shown in Figure 2.

When CS is low, the data presented to the input SDIN is shifted

MSB first into the internal shift register on the rising edge of

SCLK. Once all 16 bits of the serial data-word have been input,

the load control LDAC is strobed, and the word is latched onto

the internal data bus. The two address bits are decoded and used to

route the 12-bit data-word to the appropriate DAC data register.

Operation of CS and SCLK

The CS and SCLK pins are internally fed to the same logical OR

gate and, therefore, require careful attention during a load cycle

to avoid clocking in false data bits. As shown in the timing

diagram in Figure 2, SCLK must be halted high, or CS must be

brought high, during the last high portion of SCLK following

the rising edge that clocked in the last data bit. Otherwise, an

additional rising edge is generated by CS rising while SCLK is

low, causing CS to act as the clock and allowing a false data bit

into the input shift register. The same must also be considered

for the beginning of the data load sequence.

Coding

The AD5726 uses binary coding. The output voltage can be

calculated from the following equation:

()

4096

REFN

REFP

REFN

OUT

−

where D is the digital code in decimal.

LOAD DAC (LDAC)

When asserted, the LDAC pin is an asynchronous, active low,

digital input that transfers the contents of the input register to

the internal data bus, updating the addressed DAC output. New

data must not be programmed to the AD5726 while the LDAC

pin is low.

CLR and CLRSEL

The CLR control allows the user to perform an asynchronous

clear function. Asserting CLR loads all four DAC registers,

forcing the DAC outputs to either zero-scale (0x000) or

midscale (0x800), depending on the state of CLRSEL as shown

in Table 9. The CLR function is asynchronous and independent

of CS. When CLR returns high, the DAC outputs remain at the

clear value until LDAC is strobed, reloading the individual DAC

registers with either the data held in the input register prior to

the clear or with new data loaded through the serial interface.

Table 9. CLR/CLRSEL Truth Table

CLR

CLRSEL

DAC Registers

Zero-Scale (0x000)

Midscale (0x800)

No Change

Table 10. DAC Address Word Decode Table

DAC Addressed

DAC A

DAC B

DAC C

DAC D

Table 11. Input Register Format

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

DB12

DB13

DB14

DB15

D11

D10

AD5734R Datasheet(PDF) 14 Page - Analog Devices

AD5734R Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL