AD5734R datasheet(15/20 Pages) AD

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AD5726

Rev. 0 | Page 15 of 20

APPLICATIONS

POWER-UP SEQUENCE

To prevent CMOS latch-up conditions, powering AVDD, AVSS,

and GND prior to any reference voltages is recommended. The

ideal power-up sequence is GND, AVSS, AVDD, VREFP, VREFN, and

the digital inputs. Noncompliance with the power-up sequence

over an extended period can elevate the reference currents and

eventually damage the device. On the other hand, if the non-

compliant power-up sequence condition is as short as a few

milliseconds, the device can resume normal operation without

damage once AVDD/AVSS are powered up.

REFERENCE CONFIGURATION

Output voltage ranges can be configured as either unipolar or

bipolar, and within these choices, a wide variety of options

exists. The unipolar configuration can be either a positive (as

shown in Figure 23) or a negative voltage output. The bipolar

configuration can be either symmetrical (as shown in Figure 24)

or nonsymmetrical.

ADR01

+15V

INPUT

OUTPUT

TRIM

10kΩ

+10V OPERATION

+15V

AD5726

0.1µF║10µF

–15V

OP1177

AVDD

AVSS

VREFP

0.2µF

VREFN

Figure 23. Unipolar +10 V Operation

0.2µF

AD5726

+15V

–15V

AVDD

VREFP

VREFN

AVSS

BALANCE

100kΩ

GAIN

100kΩ

6.2Ω

0.2µF

6.2Ω

1µF

39kΩ

AD688 FOR ±10V

AD588 FOR ±5V

±5 OR ±10V OPERATION

0.1µF║10µF

Figure 24. Symmetrical Bipolar Operation

Figure 24 (symmetrical bipolar operation) shows the AD5726

configured for ±10 V operation. See the AD688 datasheet for a

full explanation of the reference operation.

Adjustments may not be necessary for many applications

because the AD688 is a very high accuracy reference. However,

if additional adjustments are required, adjust the AD5726 full-

scale first. Begin by loading the digital full-scale code (0xFFF).

Then, modify the gain adjust potentiometer to attain a DAC

output voltage of 9.9976 V. Next, alter the balance adjust to set

the midscale output voltage to 0.000 V.

The 0.2 μF bypass capacitors shown at their reference inputs in

Figure 24 should be used whenever ±10 V references are used.

Applications with single references or references to ±5 V may

not require the 0.2 μF bypassing. The 6.2 Ω resistor in series

with the output of the reference amplifier keeps the amplifier

from oscillating with the capacitive load. This has been found to

be large enough to stabilize this circuit. Larger resistor values

are acceptable if the drop across the resistor does not exceed a VBE.

Assuming a minimum VBE of 0.6 V and a maximum current of

2.75 mA, the resistor should be under 200 Ω for the loading of a

single AD5726.

Using two separate references is not recommended. Having two

references may cause different drifts with time and temperature,

whereas with a single reference, most drifts track.

Unipolar positive full-scale operation can usually be set by a

reference with the correct output voltage. This is preferable to

using a reference and dividing down to the required value. For a

10 V full-scale output, the circuit can be configured as shown in

Figure 25. In this configuration, the full-scale value is first set by

adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.

AD5726

0.2µF

0V TO –10V OPERATION

+15V

–15V

ADR01

TEMP

GND

+15V

OP1177

V+

V–

VOUT

VIN

TRIM

AVDD

VREFP

VREFN

AVSS

0.1µF║10µF

Figure 25. Unipolar −10 V Operation

Figure 25 shows the AD5726 configured for −10 V to 0 V opera-

tion. An ADR01 and OP1177 are configured to produce a −10 V

output that is connected directly to VREFP for the reference voltage.

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