Electrical Characteristics

MC13192 Technical Data, Rev. 3.2

10

Freescale Semiconductor

Figure 6 shows a typical AC parameter evaluation circuit.

Figure 6. Parameter Evaluation Circuit

Table 6. Digital Timing Specifications

(VBATT, VDDINT = 2.7 V, TA = 25 °C, frequency = 16 MHz, unless otherwise noted.

SPI timing parameters are referenced to

Figure 8.

Symbol

Parameter

Min

Typ

Max

Unit

T0

SPICLK period

125

nS

T1

Pulse width, SPICLK low

50

nS

T2

Pulse width, SPICLK high

50

nS

T3

Delay time, MISO data valid from falling SPICLK

15

nS

T4

Setup time, CE low to rising SPICLK

15

nS

T5

Delay time, MISO valid from CE low

15

nS

T6

Setup time, MOSI valid to rising SPICLK

15

nS

T7

Hold time, MOSI valid from rising SPICLK

15

nS

RST minimum pulse width low (asserted)

250

nS

J4

CLOCK Sel

1

2

MISO

R3

10k

RXD

J2

HEADER 10X2

SPI_CLK

GPIO1

L2

6.8nH

T2

2450BL15B200

R5

47k

GPIO2

R2

200

+

C2

220pF

U1

MC13192

20

22

3

5

7

19

24

18

17

4

6

8

23

21

1

2

IRQ

VDDINT

GND

PAO+

GND

CE

GPIO6

MISO

MOSI

GND

PAO-

GPIO4

GPIO5

VDDD

RFIN-

RFIN+

R1

47k

R6

47k

R4

47k

ABEL RESET

C7

10pF

+

C1

220pF

C4

9pF

C5

9pF

J3

Wake Up

1

2

ATTN

J6

SMA

2

J5

SMA

2

+

C3

220pF

GPIO2

J7

RESET

1

2

3

T1

2450BL15B200

CLKO

C8

10pF

MOSI

GPIO1

VCC

Y1

TSX-10A@16Mhz

Baud SEL

PA2

J1

MCU Interface

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

C6

0.1uF

RTXENi

L1

8.2nH

MCU RESET

CE

IRQ

RTXENi

16 MHz CLK