13192 datasheet(14/24 Pages) FREESCALE

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Pin Connections

MC13192 Technical Data, Rev. 3.2

Freescale Semiconductor

Pin Connections

Table 8. Pin Function Description

Pin #

Pin Name

Type

Description

Functionality

RFIN-

RF Input

LNA negative differential input.

RFIN+

RF Input

LNA positive differential input.

Not Used

Tie to Ground.

Not Used

Tie to Ground.

PAO+

RF Output /DC Input

Power Amplifier Positive Output. Open drain. Connect

to VDDA.

PAO-

RF Output/DC Input

Power Amplifier Negative Output. Open drain.

Connect to VDDA.

Test mode pin. Tie to Ground

Tie to Ground for

normal operation

GPIO41

Digital Input/ Output

General Purpose Input/Output 4.

See Footnote 1

GPIO31

Digital Input/ Output

General Purpose Input/Output 3.

See Footnote 1

GPIO21

Digital Input/ Output

General Purpose Input/Output 2. When gpio_alt_en,

Valid” indicator.

See Footnote 1

GPIO11

Digital Input/ Output

General Purpose Input/Output 1. When gpio_alt_en,

Idle” indicator.

See Footnote 1

RST

Digital Input

Active Low Reset. While held low, the IC is in Off Mode

and all internal information is lost from RAM and SPI

registers. When high, IC goes to IDLE Mode, with SPI

in default state.

RXTXEN2

Digital Input

Active High. Low to high transition initiates RX or TX

sequence depending on SPI setting. Should be taken

high after SPI programming to start RX or TX

sequence and should be held high through the

sequence. After sequence is complete, return

RXTXEN to low. When held low, forces Idle Mode.

See Footnote 2

ATTN2

Digital Input

Active Low Attention. Transitions IC from either

Hibernate or Doze Modes to Idle.

See Footnote 2

CLKO

Digital Output

Clock output to host MCU. Programmable frequencies

of:

16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5 kHz,

32.786+ kHz (default),

and 16.393+ kHz.

SPICLK2

Digital Clock Input

External clock input for the SPI interface.

See Footnote 2

MOSI2

Digital Input

Master Out/Slave In. Dedicated SPI data input.

See Footnote 2

MISO3

Digital Output

Master In/Slave Out. Dedicated SPI data output.

See Footnote 3

CE2

Digital Input

Active Low Chip Enable. Enables SPI transfers.

See Footnote 2

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