MC13202 Technical Data, Rev. 1.2

Freescale Semiconductor

13

A typical interconnection to a microcontroller is shown in Figure 7.

Figure 7. SPI Interface

Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock

registers and memory.

6.2.1

SPI Burst Operation

The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master

(MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the

master on the MISO line. Although an MC13202 transaction is three or more SPI bursts long, the timing

of a single SPI burst is shown in Figure 8.

Figure 8. SPI Single Burst Timing Diagram

SPI digital timing specifications are shown in Table 6.

Shift Register

Baud Rate

Generator

Shift Register

Chip Enable (CE)

RxD

MISO

TxD

MOSI

Sclk

SPICLK

MCU

MC13202

CE

1

23

4

5

6

7

8

CE

SPIC L K

T1

T2

T4

T0

SP I B urst

V alid

T5

T6

T3

V alid

T7

MIS O

MO S I

V alid