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PHN103 Datasheet(PDF) 3 Page - NXP Semiconductors |
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PHN103 Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 12 page ![]() 1997 Jun 20 3 Philips Semiconductors Product specification N-channel enhancement mode MOS transistor PHN103 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Notes 1. Ts is the temperature at the soldering point of the drain lead. 2. Pulse width and duty cycle limited by maximum junction temperature. 3. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 27.5 K/W. 4. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage (DC) − 30 V VGS gate-source voltage (DC) −±20 V ID drain current (DC) Ts =80 °C; note 1 − 8.5 A IDM peak drain current note 2 − 35 A Ptot total power dissipation Ts =80 °C − 4W Tamb =25 °C; note 3 − 2.7 W Tamb =25 °C; note 4 − 1.15 W Tstg storage temperature −65 +150 °C Tj operating junction temperature −65 +150 °C Source-drain diode IS source current (DC) Ts =80 °C − 5A ISM peak pulsed source current note 2 − 20 A SYMBOL PARAMETER VALUE UNIT Rth j-s thermal resistance from junction to soldering point 17.5 K/W |
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