56855 datasheet(3/52 Pages) FREESCALE

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56855 Technical Data, Rev. 6

Freescale Semiconductor

56855 Block Diagram

JTAG/

Enhanced

OnCE

Program Controller

and

Hardware Looping Unit

Data ALU

16 x 16 + 36

→ 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

Address

Generation Unit

Bit

Manipulation

Unit

16-Bit

DSP56800E Core

XTAL

EXTAL

Interrupt

Controller

Quad

Timer

GPIOG

CLKO

External Address

Bus Switch

External Bus

Interface Unit

RESET

IRQA

IRQB

VDD VSSIO

VDDA VSSA

External Data

Bus Switch

Bus Control

WR Enable

RD Enable

CS0-CS3[3:0] or

A0-20 [20:0]

MODEA-C or

D0-D15 [15:0]

Program Memory

24,576 x 16 SRAM

Boot ROM

1024 x 16 ROM

Data Memory

24,576 x 16 SRAM

PDB

XAB1

XAB2

XDB2

CDBR

2 SCI

GPIOE

IPBus Bridge (IPBB)

(GPIOH0-H2)

VDDIO

Decoding

Peripherals

System

Bus

Control

Memory

PAB

CDBW

CDBR

CDBW

VSS

GPIOA0-GPIOA3[3:0]

ESSI0

GPIOC

RSTO

DMA

6 channel

POR

Integration

Module

System

COP/

Watch-

dog

Time

Day

Clock

Generator

OSC PLL

IPBus CLK

COP/TOD CLK

Core CLK

56855 General Description

• 120 MIPS at 120MHz

• 24K x 16-bit Program SRAM

• 24K x 16-bit Data SRAM

• 1K x 16-bit Boot ROM

• Access up to 2M words of program memory or 8M

words of data memory

• Chip Select Logic for glueless interface to ROM and

SRAM

• Six (6) independent channels of DMA

• Enhanced Synchronous Serial Interface (ESSI)

• Two (2) Serial Communication Interfaces (SCI)

• General Purpose 16-bit Quad Timer with 1 external pin

• JTAG/Enhanced On-Chip Emulation (OnCE™) for

unobtrusive, real-time debugging

• Computer Operating Properly (COP)/Watchdog Timer

• Time-of-Day (TOD)

• 100 LQFP package

•Up to 18 GPIO

56855 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc

56855 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc

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