56855 datasheet(49/52 Pages) FREESCALE

49 / 52 page

Electrical Design Considerations

56855 Technical Data, Rev. 6

Freescale Semiconductor

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Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents

in the VDD and GND circuits.

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All inputs must be terminated (i.e., not allowed to float) using CMOS levels.

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Take special care to minimize noise levels on the VDDA and VSSA pins.

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When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.

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Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as

development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as

well as a means to assert TRST independently of RESET. Designs that do not require debugging

functionality, such as consumer products, should tie these pins together.

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The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but

requires that TRST be asserted at power on.

56855 Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc