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MAX77972 Datasheet(PDF) 52 Page - Analog Devices |
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MAX77972 Datasheet(HTML) 52 Page - Analog Devices |
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52 / 171 page ![]() MAX77972 AccuCharge + ModelGauge 1-Cell Fuel Gauge and 3A Charger with Integrated USB Type-C Detection www.analog.com Analog Devices | 52 Soft Reset Soft reset restores the MAX77972 to its power-up state, the same as if the power had been cycled. This is useful for testing different configurations without writing to nonvolatile memory. Use the following sequences to reset the IC. • Reset IC hardware by writing 000Fh to the Command register. • Wait 30ms. • Follow software implementation guide to initialize MAX77972. Pushbutton SYS Hard Reset When nChgConfig5.DATAMUX is set to 0 (default), pushbutton SYS reset feature is enabled on DATAMUX pin. Hold DATAMUX pin low for 6s to cycle the power on SYS pin for 150ms. I2C Serial Communication General Description The IC features a revision 3.0 I2C-compatible, 2-wire serial interface consisting of a bidirectional serial data line (SDA) and a serial clock line (SCL). This device relies on the controller to generate a clock signal. SCL clock rates from 0Hz to 400kHz are supported. I2C is an open-drain bus and therefore SDA and SCL require pullups. Optional resistors (24Ω) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot on bus signals. Figure 20 shows the functional diagram for the I2C based communications controller. For additional information on I2C, see the I2C Bus Specification and User Manual which is available for free through the internet. Features • I2C Revision 3.0 compatible serial communications channel • Compatible with any bus timing up to 400kHz • Does not utilize I2C clock stretching I2C Simplified Block Diagram There are three pins (aside from GND) for the I2C-compatible interface. VIO determines the logic level, SCL is the clock line, and SDA is the data line. Note that the interface cannot drive the SCL line. ep Figure 20. I2C Simplified Block Diagram 0 |
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