AD5441

Preliminary Technical Data

Rev. PrA | Page 12 of 16

BIPOLAR 4-QUADRANT MULTIPLYING

Figure 22 shows a suggested circuit to achieve 4-quadrant

by 2 and offsets the output with the reference voltage so that a

LSB) when the DAC is loaded with all ones. Therefore, the

digital coding is offset binary. The voltage output transfer

equation for various input data and reference (or signal) values

follows

where:

D is the decimal data loaded into the DAC register.

NOTES

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS

R3 AND R4.

3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

IF A1/A2 IS A HIGH SPEED AMPLIFIER.

GND

CLK

SRI

±10V

R1

LD

AD5441

AGND

C1

A1

A2

R2

μCONTROLLER

R3

20kΩ

R4

10kΩ

R5

20kΩ

Figure 22. Bipolar (4-Quadrant) Operation

INTERFACE LOGIC INFORMATION

The AD5441 has been designed for ease of operation. The

timing diagram in Figure 5 illustrates the input register loading

sequence. Note that the most significant bit (MSB) is loaded

first. Once the 12-bit input register is full, the data is transferred

to the DAC register by taking LD momentarily low.

DIGITAL SECTION

The AD5441’s digital inputs, SRI, LD, and CLK, are TTL

compatible. The input voltage levels affect the amount of

current drawn from the supply; peak supply current occurs as

the digital input (VIN) passes through the transition region. See

Figure 8 for the supply current vs. logic input voltage graph.

Maintaining the digital input voltage levels as close as possible

consumption. The AD5441’s digital inputs have been designed

with ESD resistance incorporated through careful layout and

the inclusion of input protection circuitry. Figure 23 shows the

input protection diodes and series resistor; this input structure

is duplicated on each digital input. High voltage static charges

applied to the inputs are shunted to the supply and ground rails

through forward-biased diodes. These protection diodes were

designed to clamp the inputs to well below dangerous levels

during static discharge conditions.

LD, CLK, SRI

GND

5kΩ

Figure 23. Digital Input Protection