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AD9991 Datasheet(PDF) 15 Page - Analog Devices

Part # AD9991
Description  10-Bit CCD Signal Processor with Precision Timing ??Generator
PDF  60 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9991 Datasheet(HTML) 15 Page - Analog Devices

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AD9991
–15–
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 13 shows an example CCD layout. The horizontal register
contains 28 dummy pixels, which will occur on each line clocked
from the CCD. In the vertical direction, there are 10 optical
black (OB) lines at the front of the readout and two at the back
of the readout. The horizontal direction has four OB pixels in the
front and 48 in the back.
Figure 14 shows the basic sequence layout, to be used during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the noneffective CCD
pixels. HBLK is used during the vertical shift interval.
The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers.
More elaborate clamping schemes may be used, such as adding
in a separate sequence to clamp during the entire shield OB lines.
This requires configuring a separate V-sequence for reading out
the OB lines.
V
H
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL OB LINES
2 VERTICAL OB LINES
Figure 13. Example CCD Configuration
VERTICAL SHIFT
VERT SHIFT
CCDIN
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
OPTICAL BLACK
DUMMY
EFFECTIVE PIXELS
OB
OPTICAL BLACK
HD
Figure 14. Horizontal Sequence Example
REV. 0



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