5.10 Typical Characteristics: Dynamic Performance

at TA = 25°C, VDD = 5.5 V, reference = 5.5 V, 12-bit resolution, and DAC outputs unloaded (unless otherwise noted)

Time (1

s/div)

VOUT (4 LSB/div)

LDAC (2.5 V/div)

DAC code transition from midscale – 4 LSB to midscale,

output load: 5 kΩ || 200 pF

Figure 5-36. Glitch Impulse, Rising Edge, 4-LSB Step

Time (1

s/div)

VOUT (4 LSB/div)

LDAC (2.5 V/div)

DAC code transition from midscale to midscale – 4 LSB,

output load: 5 kΩ || 200 pF

Figure 5-37. Glitch Impulse, Falling Edge, 4-LSB Step

Time (5

s/div)

Small Signal VOUT (4 LSB/div)

Large Signal VOUT (2.5 V/div)

LDAC (2.5 V/div)

DAC code transition from 408d to 3688d, typical

channel shown, output load: 5 kΩ || 200 pF

Figure 5-38. Full-Scale Settling Time, Rising Edge

Time (5

s/div)

Small Signal VOUT (4 LSB/div)

Large Signal VOUT (2.5 V/div)

LDAC (2.5 V/div)

DAC code transition from 3688d to 408d, typical

channel shown, output load: 5 kΩ || 200 pF

Figure 5-39. Full-Scale Settling Time, Falling Edge

Time (50

s/div)

-4

-2

0

2

4

6

8

10

12

14

16

18

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

Output load: 5 kΩ || 200 pF

Figure 5-40. Power-On Glitch

Time (1 ms/div)

-20

-15

-10

-5

0

5

10

15

20

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

Output load: 5 kΩ || 200 pF

Figure 5-41. Power-Off Glitch

DAC43508, DAC53508, DAC63508

SLASF08A – DECEMBER 2021 – REVISED MAY 2024

www.ti.com

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