33884 datasheet(7/21 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33884

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 105°C, unless otherwise

noted. Typical values, where applicable, reflect the approximate parameter mean with VPWR = 13 V, TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUT TIMING

Pulse Wetting Current Duration

tPULSE

3.0

Interrupt Delay Time

tINT(DELAY)

2.5

—

SCLK Frequency vs. SO Load Capacitance

200 pF

160 pF

120 pF

fSCLK

3.2

3.5

4.0

—

MHz

DIGITAL INTERFACE TIMING

Input Logic Voltage Thresholds (13)

VIN(LOGIC)

0.2 x VDD

—

0.7 x VDD

SO High State Output Voltage (IOH = 1 mA)

VOH(SO)

3.5

—

SO Low State Output Voltage (IOL = 1 mA)

VOL(SO)

—

0.4

SO Tri-State Leakage Current (CS = 0.7 VDD, VSO = 0 to VDD)

IT(SO)

-40

—

µA

SI Pull Down Current (SI = VDD)

ISI

5.0

—

µA

SCLK Input Current (0 V = VDD)

ISCLK

-10

—

µA

CS Pull-Up Current (CS = 0 V)

ICS

-25

—

-5.0

µA

RST Pull Down Current (RST = 0 V)

IRST

5.0

—

µA

INT Low State Output Voltage (IOL = 0.5 mA)

VOL(INT)

—

0.4

Input Capacitance on SCLK, SI, Tri-State, SO, CS (13)

CIN

—

Falling Edge of CS to Rising Edge of SCLK (13) (Required set-up time)

tLEAD

—

100

140

Falling Edge of SCLK to Rising Edge of CS (Required set-up time)

tLAG

—

SI to Rising Edge of SCLK (Required set-up time)

tSU2

—

Rising Edge of SCLK to SI (Required hold time)

tH2

—

SO to Rising Edge of SCLK

tSU1

125

—

Rising Edge of SCLK to Falling Edge of SO (Hold time)

tH1

125

—

SO Rise Time, SO Fall Time (CL = 200 pF)

tR(SO)

tF(SO)

—

SI, CS, SCLK Incoming Signal Rise Time (13)

tR(SI)

—

SI, CS, SCLK Incoming Signal Fall Time (13)

tF(SI)

—

Time from Falling Edge of CS to SO Low Impedance (13)

tSO(EN)

—

110

Notes

Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, SYNC, MASL. See page five.

This parameter is guaranteed by design, however, it has not been production tested.

Rise and fall time for incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

Time required for output states data to be available at SO pin.

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