33884 datasheet(10/21 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33884

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

Figure 5. SPI Parallel Interface with Microprocessor

Figure 6. SPI Serial Interface with Microprocessor

FUNCTIONAL PIN DESCRIPTION

CHIP SELECT (CS)

The MCU system selects the 33884 to receive its

communication through the Chip Select (CS) pin. With the CS

in a logic low state, command words may be sent to the

33884 via the Serial Input (SI) pin. Switch status is received

by the MCU via Serial Output (SO) pin. The falling edge of CS

enables the SO output, latches the state of the Interrupt (INT)

pin, Operating mode and the state of the external switch

inputs. The rising edge of CS disables the SO driver, resets

the INT pin to logic [1], activates the received command word,

and allows the 33884 to act upon new data obtained from

switch inputs. To avoid any spurious data, it is essential the

high-to-low and low-to-high transition of the CS signal occur

only when System Clock (SCLK) is in a logic low state.

Internal to the 33884 is an active pull-up on CS pin.

SYSTEM CLOCK (SCLK)

The System Clock (SCLK) pin clocks the internal 16-bit

Shift register. The Serial Input (SI) data is latched into the

Input Shift register on the rising edge of SCLK signal. The

Serial Output (SO) pin shifts the switch status bits out on the

falling edge of SCLK. False clocking of the Shift register must

be avoided to guarantee validity of data. It is essential the

SCLK pin be in a logic low state whenever CS makes any

transition. For this reason it is recommended, though not

necessary, the SCLK pin be commanded to a low logic state

as long as the device is not accessed (CS in logic high state).

When the CS is in a logic high state, any signal on the SCLK

and SI pin will be ignored and the SO pin is Tri-Stated (high

impedance).

SERIAL INPUT (SI)

This Serial Input (SI) pin is used for serial instruction data

input. SI information is latched into the Input register on the

rising edge of SCLK. A logic high state present at SI when

SCLK rises, programs a logic [1] into the command word on

rising edge of the CS signal. To program a complete word, 16

bits of information must be entered into the 33884. Internal to

the IC is an active pull down on the SI pin.

SERIAL OUTPUT (SO)

The Serial Output (SO) pin is the output from the Shift

transitions to a logic low state. All open switches are reported

as logic [0], all closed switches are reported as logic [1]. The

negative transition of CS will make status bit 15 available on

SO. Each successive negative clock makes the next status

bit available. The SI/SO shifting of the data follows a first-in-

first-out protocol with both input and output words transferring

the most significant bit (MSB) first.

MASTER/SLAVE (MASL)

The Master/Slave (MASL) pin is required when multiple

33884 devices are used in one module. The MASL identifies

which device will be the master or slave. MASL identification

is used during the Polling mode. In the Polling mode, the

master device has it’s internal oscillator running while the

Slave device oscillator is shutdown. While polling, the master

device wakes the slave via the Synchronization (SYNC) pin.

This feature provides minimal quiescent from the voltage

power (VPWR) and voltage digital drain (VDD) pins.

MC68HCXX

Microcontroller

33884

MOSI

16 Bit Shift Register

MISO

Parallel

Ports

SCLK

INT

SCLK

RST

INT

Microcontroller

33884

MC68HCXX

16 Bit Shift Register

Parallel

Ports

INT

SCLK

MISO

MOSI

SCLK

RST

INT

33884 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc

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