33977 datasheet(23/37 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33977

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

by status bits MOV0. Additional details are provided in the

Internal clock Calibration section.

Some applications may require a guaranteed maximum

pointer velocity and acceleration. Guaranteeing these fall

below 1.0 MHz. The frequency range of the calibrated clock

maximums requires [that deleted PV] the nominal internal

clock frequency will always be below 1.0 MHz if bit PE4 is

Logic [0] when initiating a calibration command, followed by

an 8.0 µs reference pulse. The frequency will be centered at

1.0 MHz if bit PE4 is Logic [1]. Some applications may require

a slower calibrated clock due to a lower motor gear reduction

ratio. Writing Logic [1] to bit PE2 will slow the internal

oscillator by one-third. Slowing the oscillator accommodates

a longer calibration pulse without overrunning the internal

counter - a condition designed to generate a CAL fault

indication. For example, calibration for a clock frequency of

667 kHz would require a calibration pulse of 12 µs. Unless the

internal oscillator is slowed by writing PE2 to Logic [1], a 12

s calibration pulse may overrun the counter and generate a

CAL fault indication.

Some applications may require faster pointer positioning

than is provided with the air core motor emulation feature.

Writing Logic [1] to bit PE5 will disable the air core emulation

for both gauges and provide an acceleration and deceleration

at the maximum that the velocity position ramp can provide.

Bit PE6 must always be written Logic [0] during all PECCR

writes if the device is being used to drive an MMT style motor.

Similarly, this bit must always be written as Logic [1] when

being used to control Switec style motors.

The default Pointer Position 0 (PE7 = 0) will be the farthest

counter-clockwise position. A Logic [1] written to bit PE7 will

change the location of the position 0 for the gauge to the

farthest clockwise position. The pointer will always move

towards position 0 when executing an RTZ. Exercise care

when writing to PECCR bit PE7 in order to prevent an

accidental change of the position 0 location.

Bits PE11:PE9 determine the content of the bits clocked

out of the SO pin. When bit PE11 is at Logic [0], the clocked

out bits will provide device status. If Logic [1] is written to bit

PE11, the bits clocked out of the SO pin, depending upon the

state of bits PE10:PE9, provides either:

• Accumulator information and detection status during

the RTZ (PE10 Logic [0])

• Real time pointer position location at the time CS goes

low (PE10 Logic [1] and PE9 Logic [0]), or

• The real time step position of the pointer as described

in the velocity Table 6 (PE10 and PE9 Logic [1]).

Additional details are provided in the SO Communication

section.

If bit PE12 is Logic [1] during a PECCR command, the

state of PE11:PE0 is ignored. This is referred to as the null

command and can be used to read device status without

affecting device operation.

The bits in Table 9 are write-only.

Null Command for Status Read (PE12) Bit D12

• 0 = Disable

• 1 = Enable

Status Select (PE11) Bit D11

This bit selects the information clocked out of the SO pin.

• 0 = Device Status (the logic states of PE10, and PE9

are don’t cares)

• 1 = RTZ Accumulator Value, Gauge Pointer position, or

Gauge Velocity ramp position (depending upon the

logic states of PE10, and PE9)

RTZ Accumulator or Pointer Status Select (PE10) Bit D10

This bit is recognized only when PE11 = 1.

• 0 = RTZ Accumulator Value and status

• 1 = Pointer Position or Speed

Pointer Position or Pointer Speed Select (PE9) Bit D9

This bit is recognized only if PE11 and PE10 = 1.

• 0 = Gauge Pointer Position

• 1 = Gauge Pointer Speed

(PE8) Bit D8

This bit must be transmitted as Logic [0] for valid PECCR

commands.

Position 0 Location Select (PE7) Bit D7

This bit determines the Position 0 of the gauge. RTZ

direction will always be to the position 0.

• 0 = Position 0 is the most CCW (counterclockwise)

position

• 1 = Position 0 is the most CW (clockwise) position

Motor Type Selection (PE6) Bit D6

• 0 = MMT Style (coil phase difference = 90°)

• 1 = Switec Style (coil phase difference = 60°)

Table 9. Power, Enable, Calibration, and Configuration Register (PECCR)

Address 000

Bits

D12

D11

D10

Read

–

Write

PE12

PE11

PE10

PE9

PE7

PE6

PE5

PE4

PE3

PE2

PE0

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