Philips Semiconductors

Product specification

SA1630

IF quadrature transceiver

1998 Jul 21

12

STROBE pin should be low during power up to guarantee a proper

reset. These default states are shown in Table 2.

Reference Divider

The reference divider can be programmed to four different division

ratios (:8, :11, :22, :44), see registers r0, r1; default setting: divide by

22.

Main Divider

divided by two and then fed to the main divider (:N). The main

divider is a programmable 9 bit divider, the minimum division ratio is

divide by 64. The division ratio is binary coded and set in the

registers n0 to n8. The default setting is a divide by 352.

At the completion of a main divider cycle, a main divider output is

generated which will drive the phase detector.

Phase Detector

The phase detector is a D-type flip-flop phase and frequency

detector shown in Figure 5. The flip-flops are set by the negative

edges of the output signals of the dividers. The rising edge of the

signal L will reset the flip-flops after both flip-flops have been set.

Around zero phase error this has the effect of delaying the reset for

1 reference input cycle. This avoids non-linearity or deadband

around zero phase error. The flip-flops drive on-chip charge pumps.

A source current from the charge pump acts to increase the VCO

frequency; a sink current acts to decrease the VCO frequency.

Current Setting

The charge pump current is defined by the current set between the

This current can be set by an external resistor to be connected

setting resistor) can be calculated with the formula

R

V

31.2

mA

(44.87K for 3V)

Charge Pumps

The charge pumps at pin CP are driven by the phase detector and

the current value is determined by the binary value of the charge

pumps register CN = c2, c1, c0, default .4mA. The active charge

pump current is typically:

|I

Lock Detect

The output LOCK is H when the phase detector indicates a lock

condition. This condition is defined as a phase difference of less

than

Test Modes (Synthesizer, Transmit Mixer)

The LOCK output is selectable as a test output. Bits x0, x1 control

the selection, the default setting is normal lock output as described

in the Lock detect section. The selection of a Bit x0, x1 combination

has a twofold effect: First it routes a divider output signal to the

LOCK pin, second it disables mixer stages in the transmit path.

Setting x0,1 = 11 disables both transmit path mixers. This mode can

be used to prevent the transmitter from producing an IF output

signal even if the transmit part is powered on. This can be used to

simplify the control timing while commanding the transmit and

receive simultaneously without the transmit part causing

interference.

Table 1. Test Modes

x0

x1

Synthesizer Signal

Transmit Mixer

x0

x1

yg

at LOCK Pin

Q-mixer

I-mixer

0

0

normal lock detect

on

on

1

0

divider ratio

off

on

0

1

on

off

1

1

main divider output, that goes to

the phase detector

off

off