SA1630 datasheet(2/22 Pages) PHILIPS

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Philips Semiconductors

Product specification

SA1630

IF quadrature transceiver

1998 Jul 21

853–2049 19763

DESCRIPTION

The SA1630 is a 70–400 MHz I/Q transceiver for wireless LAN.

The Receive Path contains a digitally gain controlled linear IF

amplifier, a pair of quadrature down conversion mixers and a pair of

baseband amplifiers. The transmit path contains a pair of quadrature

up conversion mixers that transposes a quadrature baseband input

signal up to IF frequency. An external VCO signal is divided

internally and provides quadrature local oscillator signals for the

mixers. Another divider chain, reference divider and phase detector

are provided to avoid the need for an external synthesizer. To keep

power consumption to a minimum the transmit, receive and local

oscillator functions can be powered down under digital control.

FEATURES

• Low supply voltage operation of 2.7V for main chip and 2.9V for

charge pump.

• Low current consumption: 33.5 mA in RX, 26.5 mA in TX, typical

at 3V.

• Flexible power up/down options.

• Optional 2.5V regulated reference voltage available during

transmit.

• Input IF frequency range of 70–400 MHz.

• Internal IF PLL for synthesizing the local IF oscillator signal.

• Bandwidth of baseband Tx inputs is 20 MHz and that of baseband

Rx outputs is 8.5MHz.

• Designed for IEEE 802.11 wireless LAN using Direct Sequence

Spread Spectrum modulation.

• Control registers power up in a default state.

• Only a standard reference input frequency required, choice of 8,

11, 22 or 44 MHz.

• Digital gain control of 70 dB in steps of 2 dB.

• Rx Baseband amplifiers are capable of driving 1kW ||15pF

• Rx Baseband o/p’s clamp symmetrically, above 1Vp–p in order to

prevent dc bias shift under overdrive conditions.

• Package: LQFP–48, PCMCIA compatible

APPLICATIONS

• IF circuitry for IEEE 802.11 DSSS wireless LAN.

• Applications for high speed wireless data.

BE Package

13 14

15 16 17 18 19

21 22 23 24

SR01549

GC0

GC1

GC2

GC3

GC4

GC5

GNDCP

DATA

CLOCK

STROBE

LO_INX

LO_IN

GNDRx

CLK IN

CLKINX

GNDRX

VCCRx

PLL_ON

Rx_ON

GNDHDR

LOCK

Figure 1.

Pin Configuration

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

DWG #

48–Pin Plastic Low Profile Quad Flat package

–40 to +85

°C

SA1630BE

SOT313–2

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