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XRT86VL32 Datasheet(PDF) 52 Page - Exar Corporation |
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XRT86VL32 Datasheet(HTML) 52 Page - Exar Corporation |
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52 / 174 page ![]() XRT86VL32 47 DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. V1.2.0 1 TxIMODE[1] R/W 0 Transmit Interface Mode selection This bit determines the transmit interface speed. The exact function of these two bits depends on whether Multiplexed mode is enabled or dis- abled. Table 28 and Table 29shows the functions of these bits for non- multiplexed and multiplexed modes.: 0 TxIMODE[0] R/W 0 TABLE 27: TRANSMIT INTERFACE CONTROL REGISTER (TICR) HEX ADDRESS:0Xn120 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION TABLE 28: TRANSMIT INTERFACE SPEED WHEN MULTIPLEXED MODE IS DISABLED (TXMUXEN = 0) TXIMODE[1:0] TRANSMIT INTERFACE SPEED 00 2.048Mbit/s. (Base Rate) Transmit Backplane interface signals include: TxSERCLK is an input or output clock at 2.048MHz TxMSYNC is the superframe boundary at 2ms TxSYNC is the single frame boundary at 125 us TxSER is the base-rate data input 01 2.048Mbit/ (High-speed MVIP Mode) Transmit Backplane interface signals include: TxSERCLK is an input clock at 2.048MHz TxMSYNC will become the high speed input clock at 2.048MHz to input high-speed data TxSYNC indicates the single frame boundary TxSER is the high-speed data input 10 4.096Mbit/s High-speed mode: Transmit Backplane interface signals include: TxSERCLK is an input clock at 2.048MHz TxMSYNC will become the high speed input clock at 4.096MHz to input high-speed data TxSYNC indicates the single frame boundary TxSER is the high-speed data input 11 8.192Mbit/s High-speed mode: Transmit Backplane interface signals include: TxSERCLK is an input clock at 2.048MHz TxMSYNC will become the high speed input clock at 8.192MHz to input high-speed data TxSYNC indicates the single frame boundary TxSER is the high-speed data input |
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