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SAA2521 Datasheet(PDF) 8 Page - NXP Semiconductors |
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SAA2521 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 28 page ![]() August 1993 8 Philips Semiconductors Preliminary specification Masking threshold processor for MPEG layer 1 audio compression applications SAA2521 Power-down Mode Switching When the potential on the RESET pin (pin 23) is held HIGH for at least 5TCLK24 clock periods, the device will be reset after which it will operate in its decoding mode. The power-down mode is activated when the PWRDWN pin (pin 30) is held HIGH. The 3-state buffers will be set to a high impedance while the normal outputs will retain the state attained prior to this mode being entered. This mode can only be used if other associated circuits react accordingly. The power-down mode is de-activated by a reset action. Fig.5 shows the operation for the power-down mode switching. Table 1 Resolution selection. RESOL1 RESOL0 RESOLUTION 0 0 16-bits 0 1 18-bits 1 0 14-bits 1 1 15-bits Fig.5 Power-down mode switching. TrH > 5TCLK24 = 210 ns (for CLK24 = 24.576 MHz) minimum time RESET HIGH MEA659 - 1 sleep mode active PWRDWN RESET t rH |
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