XRT8000IP datasheet(14/24 Pages) EXAR

14 / 24 page

XRT8000

Rev. 1.11

CR5 Register (Power On State = “00000”)

D0 : ( PL1/8) :

Select the divider by 8 for PLL1,

PL1/8 = “1” CLK1 output frequency is divided by 8.

PL1/8 = “0” CLK1 output frequency is as per table 4.

D1 : ( PL2/8) :

Select the divider by 8 for PLL2,

PL2/8 = “1” CLK2 output frequency is divided by 8.

PL2/8 = “0” CLK2 output frequency is as per table 5.

D2 : ( CLK2EN) , PLL2:

Output enable bit,

CLK2EN = “1” CLK2 output is enabled.

CLK2EN = “0” CLK2 output is Tri State D.

D3 : ( CLK1EN) , PLL1:

Output enable bit,

CLK1EN = “1” CLK1 output is enabled.

CLK1EN = “0” CLK1 output is Tri State D.

D4 : ( SYNCEN) , 8kHz SYNC enable bit:

SYNCEN = “1” SYNC output is enabled.

SYNCEN = “0” SYNC output is Tri State D.

CR6 to CR7 Register

Address

Data In

Data Out

R/W

HiZ

SDO

SDI

SCLK

CSB

Figure 4. Serial Processor Interface Data Structure

Note

A3, A4 and A5 always Low.

A6 Do not care.

R/W bit = 1 for a read operation

2 for a write operation

D5, D6 and D7 always Low

SERIAL INTERFACE

The serial interface is a simple four wire interface that is

compatible with many of the microcontrollers available in

the market. This interface consists of the following

signals:

CSB

Chip Select (Active Low)

SCLK

Serial Clock Input

SDI

Serial Data Input

SDO

Serial Data Output

XRT8000IP Datasheet(PDF) 14 Page - Exar Corporation

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