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A5000 Datasheet(PDF) 4 Page - NXP Semiconductors |
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A5000 Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 25 page ![]() NXP Semiconductors A5000 EdgeLock Secure Authenticator 2.3 Features in detail Categories A5000 Security certification CC EAL6+ (HW+OS) x JavaCard version 3.0.5 x GlobalPlatform specification version GP 2.3.1 x ECDSA x ECDH x ECC Crypto Schemes ECDHE x ECC NIST P256 x Supported Elliptic Curves ECC NIST P384 x 3DES (2K, 3K) x Symmetric Crypto Algorithm AES (128, 192, 256) x AES Modes CBC, ECB,CTR,GCM,CCM x Hash Function SHA-256, SHA-384 x MAC HMAC, CMAC, GMAC x Key Derivation (KDF) HKDF x Secure Channel Secure Channel Host-SA (Platform SCP) x TRNG NIST SP800-90B, AIS31 DRBG NIST SP800-90A, AIS20 Memory reliability up to 100 million write cycles / 25 years x User Memory 8kB Pre-Provisioned x Interfaces I2C Target, up to 1 Mbit x Power-Down (with state retention), 460 µA (I2C) Disabled [1] Power saving modes Deep Power-Down (no state retention), <5 µA x Temperature Extended, -40 °C - 105 °C, see Section 1.3 x Packaging Plastic QFN, 3 mm x 3 mm (HX2QFN20) with max 0.33 mm height x Table 2. A5000 configuration [1] Power down mode can be enabled in custom part configuration. A5000 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 1.5 — 8 July 2024 Document feedback 667615 4 / 25 |
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