SAA7380GP datasheet(10/60 Pages) PHILIPS

10 / 60 page

1996 Apr 25

Philips Semiconductors

Preliminary speciﬁcation

Error correction and host interface IC for

CD-ROM (ELM)

SAA7380

FUNCTIONAL DESCRIPTION

The SAA7380 is comprised of four main blocks; a CD

player interface, an error corrector, a host interface and a

memory manager. These four blocks operate in parallel.

All receive and send data to the buffer memory via the

memory manager. A 36-kbit on-chip SRAM has been

incorporated to allow high-speed data read operations for

the error corrector.

The SAA7380 performs simultaneous data input buffering,

error correction and host data transfer.

7.1

CD-DSP interface and data input

The input data is synchronized, decoded, and written to

the buffer RAM. The input data format is software

programmable.

The synchronization is achieved using a sync detector and

a sync interpolator. The sync detector detects the sync

pattern in every sector while the interpolator avoids sync

loss when no sync is found. The detector and interpolator

can be individually enabled and disabled under software

control.

After decoding, each full sector of data (2352 bytes)

comprising sync, header, sub-header and parity fields is

written to the buffer RAM.

7.2

Error correction and EDC check

Error correction and detection is performed on each sector

after it is written to the buffer RAM.

The SAA7380 buffers flag and data of sectors to be

corrected in a 9-bit, 4096 words on-chip RAM memory.

For erasure correction, no external 9-bit memory is

required.

The standard error correction algorithm can be

programmed, and supports Mode 1 and Mode 2, Form 1

and Form 2 discs.

After error correction, an electronic data check is

executed.

When this EDC check is also complete, the sector header

and sub-header is written to 8 header registers, and a

decode complete interrupt is generated.

The microcontroller can then read the decoder status, the

sector header and sub-header and the sector start

address from the SAA7380.

7.3

Host interface

The host interface controls data transfers between the

SAA7380 and an external microcontroller. The host

interface can be programmed to operate in three modes.

In the Sanyo compatibility mode the host interface is

functionally compatible with the Sanyo LC89510 block

decoder. In the Oak compatibility mode the host interface

is functionally compatible with the Oak OTI-012 controller

chip in enhanced mode.

In the ATAPI mode the interface meets the ATA Program

Interface specification.

7.4

Subcode channel Q-to-W buffering

As well as buffering the main data, the SAA7380 can also

be used to buffer R-to-W subcode data in buffer memory.

Two buffer modes exist, raw mode and cooked mode. In

the raw mode, data is written to an external RAM without

any processing being performed. In the cooked mode, the

Q-channel data is extracted, the Q-channel CRC is

calculated, the R-to-W data is de-interleaved and the

residues of each R-to-W frame are calculated. These

residues make it easier to correct errors in the data.

7.5

External buffer memory

It is possible to use the SAA7380 with different external

RAM memories. From 0 to 128 kbyte SRAMs or to 16-Mbit

DRAMs are possible. Memories may be nibble or byte

wide (allowing 2, 8 or 16 Mbits). Selection is performed

under software control.

Unique to the SAA7380 is its ability to work with partly

defective DRAMs. The SAA7380 offers the possibility to

use a DRAM with bytes in error.

A RAM test is executed under microcontroller control. This

RAM test indicates defective segments to the

microcontroller which keeps a list of which bad sectors to

avoid. The list can be stored in the buffer memory and/or

the microcontrollers own memory.

7.6

Sub-CPU registers

This section describes the registers in the SAA7380. The

operation of the registers varies depending on whether

they are being read from or written to, and the host mode

selected.

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