SAA7380GP datasheet(28/60 Pages) PHILIPS

28 / 60 page

1996 Apr 25

Philips Semiconductors

Preliminary speciﬁcation

Error correction and host interface IC for

CD-ROM (ELM)

SAA7380

7.9.2.3

HCON

Table 28 HCON register bits

Note

1. Where X = don’t care.

This is the host configuration register. Resetting SAA7380 clears this register.

BIT 7(1)

BIT 6(1)

BIT 5(1)

BIT 4(1)

BIT 3

BIT 2

BIT 1

BIT 0

DTS

SDRQ

LOHI

DMA16

Bit DTS is the suspend transfer bit. Setting this bit HIGH

suspends non-DMA transfers and allows the host to

access the COMIN and SBOUT registers. During DMA

transfers this bit has no effect.

If SDRQ is LOW and the SELRQ pin is LOW then DMA

transfer is selected otherwise non-DMA transfer is

selected.

The pseudo 16-bit DMA read transfer is selected by setting

bit DMA16 HIGH. DMA transfer must also be selected for

this mode to operate. host writes are always 8-bit and are

not affected by this bit.

The LOHI bit when HIGH causes the pseudo 16-bit DMA

transfer to be a LOW byte followed by a HIGH byte. Setting

it LOW causes the sequence to be a HIGH byte followed

by a LOW byte. If the 16-bit DMA mode is not selected

then this bit has no effect.

7.9.3

ATAPI MODE

The following registers are accessible by the ATAPI host.

Most of these registers are identical to the sub-CPU

registers with the same name.

Table 29 ATAPI registers

ADDRESS

WRITE HWR

READ HRD

WIDTH

CS2

CS1

DA2

DA1

DA0

10000

DATA

10001

AFEAT

AERR

10010

AINTR

10011

ASAMT

10100

DBCL

10101

DBCH

10110

ADRSEL

10111

ACMD

ASTAT

01110

ADCTR

Alt Status

01111

reserved

ADRADR

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